Packaging semiconductor devices present several problems. One such problem is encountered when using an interposer-silicon-substrate architecture such as an embedded package that is widely used in mobile applications. In this architecture, after a system on chip (SOC) is attached to the substrate, an interposer is attached to the substrate through a package on package (PoP) interconnect and then mechanically coupled to the bottom package with a molding compound or epoxy materials.
The interposer-silicon-substrate architecture is typically implemented as a result of (i) the flexibility of using the interposer to translate the fine PoP pitch, custom pattern on the substrate to standard pitch, and pattern on top of the interposer to accommodate standard and off-the-shelf memory packages; and (ii) the symmetrical mechanical configuration of this architecture (i.e., an organic substrate-silicon-organic substrate) to control the overall package warpage for standard surface mount processes.
This architecture, however, also has some major disadvantages. One major disadvantage of the interposer-silicon-substrate architecture is the thermal performance as the SOC die is embedded in the molding or epoxy compound underneath the organic interposer. For example, the thermal conduction through the interposer can be improved by adding thermal vias and/or reducing the layer count. Nonetheless, the thermal conductivity of typical molding or epoxy compounds still remain very low (e.g., <1 W/mK), including a high-K molding or epoxy materials that have at best a thermal conductivity of roughly 2 W/mK. As such, this major disadvantage of the interposer-silicon-substrate architecture elicits the bottleneck for the thermal performance of the SOC and thus produces overheating issues.
Accordingly, there is a need to form an improved embedded die package with improved thermal performance without scaling down the performance of the SOC.